Warning: Design 'FABSCALAR' has '10' unresolved references. For more detailed information, use the "link" command. (UID-341)
Information: Updating design information... (UID-85)
Warning: Design 'FABSCALAR' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
 
****************************************
Report : qor
Design : FABSCALAR
Version: F-2011.09-SP2
Date   : Tue May 15 12:36:55 2012
****************************************


  Timing Path Group 'clock'
  -----------------------------------
  Levels of Logic:            77.0000
  Critical Path Length:       49.8655
  Critical Path Slack:         0.0047
  Critical Path Clk Period:   50.0000
  Total Negative Slack:        0.0000
  No. of Violating Paths:      0.0000
  Worst Hold Violation:        0.0000
  Total Hold Violation:        0.0000
  No. of Hold Violations:      0.0000
  -----------------------------------

  Timing Path Group 'default'
  -----------------------------------
  Levels of Logic:            30.0000
  Critical Path Length:       33.2261
  Critical Path Slack:        16.2839
  Critical Path Clk Period:       n/a
  Total Negative Slack:        0.0000
  No. of Violating Paths:      0.0000
  Worst Hold Violation:        0.0000
  Total Hold Violation:        0.0000
  No. of Hold Violations:      0.0000
  -----------------------------------


  Cell Count
  -----------------------------------
  Hierarchical Cell Count:         32
  Hierarchical Port Count:      23057
  Leaf Cell Count:              79531
  Buf/Inv Cell Count:           12579
  CT Buf/Inv Cell Count:            0
  Combinational Cell Count:     66878
  Sequential Cell Count:        12653
  Macro Count:                      0
  -----------------------------------


  Area
  -----------------------------------
  Combinational Area:     670853.8374
  Noncombinational Area:  312868.4520
  Net Area:               153451.7314
  -----------------------------------
  Cell Area:              983722.2894
  Design Area:           1137174.0208


  Design Rules
  -----------------------------------
  Total Number of Nets:         89822
  Nets With Violations:             0
  Max Trans Violations:             0
  Max Cap Violations:               0
  -----------------------------------


  Hostname: ivycreek.ece.Virginia.EDU

  Compile CPU Statistics
  -----------------------------------------
  Resource Sharing:                  0.2969
  Logic Optimization:              209.1094
  Mapping Optimization:            299.0916
  -----------------------------------------
  Overall Compile Time:            537.2333
  Overall Compile Wall Clock Time: 1327.3804

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